Atlas3 Broadcom Silicon Host Card PCIe 6.0

Serial Cables Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64)

November 2, 2026 — admin
Serial Cables Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64), a Broadcom PEX90064 PCIe 6.0 host adapter with four MCIO x8 connectors and a Gen6 straddle-mount x16 connector

The Serial Cables Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64) is a PCIe 6.0 switch-based host adapter built on the Broadcom PEX90064 Atlas3 switch — up to 64 lanes and 40 ports fanned out to four MCIO x8 connectors and a PCIe straddle-mount connector, with an onboard MCU CLI for switch configuration, telemetry, and firmware management.

What it is

The Serial Cables Atlas3 64-A0 Host Adapter Card is a PCIe Gen 6 adapter built around the Broadcom PEX90064 Atlas3 switch, supporting up to 64 PCIe lanes and 40 ports. It provides flexible connectivity between a host system and external PCIe devices through four right-angle MCIO x8 (SFF-TA-1016) connectors and one PCIe straddle-mount connector. It is manufactured by Serial Cables, LLC (Englewood, Colorado, USA), and its part number / SKU is PCI6-AD-x16HI-BG6-64.

The adapter supports both unmanaged operation (without managed firmware) and managed operation (with firmware). An onboard microcontroller provides command-line interface (CLI) access over USB Type-C for switch configuration, device management, diagnostics, and troubleshooting, and the switch adds non-transparent port support, peer-to-peer data transfers, DMA, and PCIe hot-plug functionality. Gen 6 operation uses PAM-4 signaling with FLIT mode and Forward Error Correction (FEC) on Broadcom’s ‘Talon 5’ SerDes.

In one sentence: the Atlas3 64-A0 Host Adapter Card is a Broadcom PEX90064-based PCIe 6.0 host adapter that fans a host slot out to four MCIO x8 cable connectors and one straddle-mount x16 device connector, with dual USB-C management, per-connector PERST#/clock/I²C sidebands, and an MCU CLI for full switch control — managed or unmanaged.

Serial Cables positions the card as a way to begin Gen6 testing without waiting for Gen6-native host platforms: installed in an existing Gen5 system, the card provides full Gen6 connectivity downstream of the switch, so endpoints behind the Atlas3 — JBOFs, EDSFF SSDs, or add-in cards on expansion fixtures — train and run at Gen6 even though the host itself is a generation behind.

Serial Cables Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64), a Broadcom PEX90064 PCIe 6.0 host adapter with four MCIO x8 connectors and a Gen6 straddle-mount x16 connector
Serial Cables Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64).

Why it exists

PCIe validation has traditionally been gated on the host: traffic is routed through the CPU and chipset, so testing Gen6 devices meant waiting for Gen6-capable motherboards, CPUs, and BIOS support. A switch-based host adapter breaks that dependency by making the switch — not the host — the Gen6 boundary. The Atlas3 64-A0 exists so that engineers can fan out up to 64 lanes of Gen6 connectivity to external devices from a system they already own, with per-connector control of reset, reference clocks, and sideband access that a bare motherboard slot cannot provide. Its intended audience is validation and qualification engineers doing Gen6 device bring-up, storage expansion testing, and add-in-card integration who need switch-level visibility — link status per port, error counters, register access, firmware control — rather than a passive slot.

Key facts

  • Product name: Serial Cables Atlas3 64-A0 Host Adapter Card
  • Part number / SKU: PCI6-AD-x16HI-BG6-64
  • Manufacturer: Serial Cables, LLC (Englewood, Colorado, USA)
  • Category: PCIe 6.0 switch-based host adapter card
  • PCIe switch: Broadcom PEX90064 Atlas3 — up to 64 lanes, up to 40 ports
  • Downstream connectivity: 4 × right-angle MCIO x8 (SFF-TA-1016) + 1 × PCIe Gen6 straddle-mount connector
  • Operating modes: Managed and unmanaged
  • Advanced PCIe features: Non-transparent ports, peer-to-peer transfers, DMA channels, hot-plug, Dynamic Port Reconfiguration (DPR)
  • Management: Onboard MCU with USB-C CLI; second USB-C for Atlas3 I²C slave and switchable SDB/Smart UART debug
  • Power: Host PCIe slot power, or auxiliary PCIe 12 V 2×6 input supplying up to 75 W to the straddle-mount device
  • Maximum power consumption: 65 W (Gen6 x64 links, excluding power supplied to the straddle-mount connector)
  • Operating temperature: 0 °C to +40 °C
  • Dimensions: 209 × 136 × 44 mm (L × H × T), including heatsink
  • Quarch Ready
  • Price: $5,995 (list)
  • Documentation: Technical Manual Revision 1.1 (November 2026)

Hardware specifications

Parameter Specification
Part number PCI6-AD-x16HI-BG6-64
PCIe switch Broadcom Atlas3 PEX90064
PCIe generation PCIe Gen 6 (64 GT/s, FLIT mode with FEC)
PCIe lanes Up to 64 lanes
PCIe ports Up to 40 ports
Operating modes Managed and unmanaged
MCIO connectors 4 × right-angle MCIO x8 (SFF-TA-1016)
PCIe device interface PCIe Gen6 straddle-mount connector
Management interfaces 2 × USB Type-C — Atlas3 debug/UART (CN6) and onboard MCU CLI (CN7)
Auxiliary power PCIe 12 V 2×6 connector; up to 75 W available to the straddle-mount connector
Maximum power consumption 65 W (Gen6 x64 links, excluding straddle-mount power)
Operating temperature 0 °C to +40 °C
PCB dimensions 209 × 136 × 44 mm (L × H × T), including heatsink

Connectors, lane assignments, and port mapping

Designator Connector type Function / description
CN1 PCIe Gen6 straddle-mount Provides a PCIe connection for a compatible device; up to 75 W with auxiliary power
CN2 MCIO x8 (SFF-TA-1016) Routes PCIe lanes 40–47
CN3 MCIO x8 (SFF-TA-1016) Routes PCIe lanes 16–23
CN4 MCIO x8 (SFF-TA-1016) Routes PCIe lanes 32–39
CN5 MCIO x8 (SFF-TA-1016) Routes PCIe lanes 24–31
CN6 USB Type-C Atlas3 I²C slave interface and switchable SDB/Smart UART interface
CN7 USB Type-C Onboard MCU command-line interface (CLI)
CN8 PCIe 12 V 2×6 auxiliary power Powers the adapter and cooling assembly; supplies up to 75 W to the straddle-mount connector

Each MCIO x8 connector carries eight PCIe lanes plus sideband signals: four dedicated PCIe HCSL reference-clock outputs (pins A8/A9, A11/A12, A26/A27, A29/A30), two dedicated I²C interfaces (pins B8/B9 and B26/B27), and four PERST# signals (pins B11, B12, B29, B30).

The auxiliary power connector pinout provides twelve 12 V pins (1–6), twelve ground pins (7–12), and four sideband signals: CARD_CBL_STABLE (S1), CARD_CBL_PRES# (S2), SENSE0 (S3), and SENSE1 (S4).

The card identifies interfaces by station, port, and connector (CON) number. Each station supports up to 16 PCIe lanes:

Interface Station Port number CON number
PCIe straddle-mount 0 0 8
Internal MCIO (upper) 1 16 5 / 4
Internal MCIO (lower) 1 24 7 / 6
External MCIO (upper) 2 32 0 / 1
External MCIO (lower) 2 40 2 / 3
PCIe golden finger 3 48 N/A

For register-level access, each port’s register block is offset by 0x8000. Base addresses on this card: straddle-mount Port 0 at 0x60800000, internal MCIO Port 16 at 0x60880000, external MCIO Port 32 at 0x60900000, and golden finger Port 48 at 0x60980000.

LED indicators

System status LEDs

LED ID Color Description
LED13 Red System error indicator — second watchdog-timer expiration, Built-In Self-Repair (BISR) error, firmware signature-authentication failure, or double-bit ECC errors
LED14 Blue Atlas3 heartbeat — blinks when managed firmware is running normally; solid on when unmanaged firmware is loaded
LED15 Green MCU status — blinks when the MCU firmware is active and responding

Link speed LEDs (blue) — each LED reflects the first port of its interface and is solid on when that port is linked at Gen6: LED12 (golden finger), LED10 (external MCIO), LED9 (internal MCIO), LED11 (straddle-mount). Use showport for detailed negotiated speed and width.

Link width LEDs (red) — these remain off when the expected link width is achieved: LED1 (golden finger), LED3/LED4 (external MCIO), LED5/LED6 (internal MCIO), LED2 (straddle-mount). A lit width LED indicates the port trained below its expected width; showport reports the link as Degraded.

Power

The card supports two power configurations. Host PCIe slot power is sufficient when no device is connected to the straddle-mount connector — if testing only devices on the MCIO connectors, auxiliary power is not required. When a device is installed in the straddle-mount connector, the PCIe 12 V 2×6 auxiliary input (CN8) powers the adapter and its cooling assembly and supplies up to 75 W to the straddle-mount device. Serial Cables’ product documentation specifies a 12 V / 20 A, 500 W independent supply that is 12VHPWR-compliant (16-pin ATX 3.0+) for the auxiliary input. Power down the host system and disconnect external supplies before installing, removing, or re-cabling the card, and never connect or disconnect power cables while the system is energized.

Key features

  • Broadcom PEX90064 Atlas3 switch: up to 64 Gen6 lanes and 40 ports, with FLIT mode and FEC for 64 GT/s PAM-4 operation.
  • Four MCIO x8 + one straddle-mount x16: cable connectivity to JBOFs, direct-attached EDSFF SSDs, and slot-expansion fixtures, plus a direct edge-based device connection — all from one card.
  • Managed and unmanaged operation: run without managed firmware for transparent fanout, or load managed firmware for higher-level switch functions.
  • Advanced PCIe functionality: non-transparent ports, true peer-to-peer data transfer, DMA channels, and hot-plug support.
  • Dynamic Port Reconfiguration (DPR): internal and external MCIO interfaces can support different link widths — including multiple x2 connections — without a full switch reset.
  • Full MCU CLI over USB-C: firmware updates, register access, per-port link status, error counters, live LTSSM monitoring, Gen6 FLIT error-rate diagnostics, per-port link-speed control, reference-clock and spread-spectrum control, FLIT configuration, SMBus/I3C/MCTP sideband access, and board diagnostics.
  • Gen6 testing without a Gen6 host: installed in an existing Gen5 system, the switch provides full Gen6 connectivity downstream.

Gen6 JBOF connectivity

The host adapter connects to an external 8-bay E3 JBOF enclosure using MCIO6-8X-2X8B Y-cables, giving access to eight single-port PCIe x4 E3 SSDs through the adapter’s MCIO interfaces, with the Y-cables distributing the PCIe connections to the enclosure. The manual’s configuration table lists the PCI5-ENC8-E3-08 8-bay E3 JBOF as the target system; Serial Cables documents the same Y-cable scheme against its Gen6 HYDRA 8-Bay Passive E3 JBOF (PCI6-ENC8-E3-08) for its other Atlas3 host cards.

Direct-attached EDSFF SSDs

EDSFF SSDs can be connected directly to the adapter’s MCIO interfaces without an external enclosure, using the MCIO6-8X-EDSFFX2-1X4 cable. This configuration supports individual storage devices in E1.S, E1.L, E2, or E3 form factors for bench testing and drive qualification.

PCIe Gen6 slot expansion

The card can extend PCIe connectivity to two external add-in card slots using MCIO-connected expansion adapters. Two MCIO x8 ports connect to one PCI6-AD-MX8-X16 expansion adapter over MCIO6-8X-8X-xM cables, and each adapter provides a physical PCIe Gen6 x16 slot — so one 64-A0 host card supports two expansion adapters for add-in-card testing outside the host chassis.

Command-line interface (CLI)

The onboard MCU provides command-line access for switch configuration, diagnostics, and firmware management over CN7 (USB Type-C). CN6 is not used for the standard MCU CLI — it exposes the Atlas3 I²C slave interface and a selectable SDB/Smart UART path instead. To connect: attach a USB-C cable from the host computer to CN7, identify the assigned COM port in Device Manager, and open a serial terminal (Tera Term, PuTTY, or equivalent); a successful connection displays the Cmd> prompt.

The CLI can monitor temperature, critical voltages, fan speed, power consumption, and PCIe link status; access switch and port registers; manage Atlas3 and MCU firmware updates; control PCIe reference clocks and connector reset signals; and run board-level diagnostics.

Command Description
fdl Upgrade Atlas3 unmanaged (mini, main) or managed (fw) firmware, or onboard MCU firmware (mcu), via XMODEM
lsd Display temperature, critical voltages, fan speeds, and board power consumption
mw Write a 32-bit value to a specified register within the Atlas3 switch
dr Dump switch-level registers for diagnostics or debugging
dp Dump port-specific switch registers for the selected port (0–111)
df Dump the contents of the switch’s onboard flash memory
conrst Send a 300 ms PERST# reset pulse to selected MCIO or straddle-mount interfaces, optionally per channel (a/b)
showport Display link status and connection details for USP/DSP ports
bist Run the onboard Built-In Self-Test across I²C devices
setmode Load the SBR configuration for Gen6 precoding and MCIO bifurcation (modes 1–8)
showmode Display the current operating mode of the host card
spread Configure the PCIe clock spread-spectrum setting
clk Enable or disable the PCIe reference-clock outputs
sdb Set the MCU SDB port state (on/off) for external debug-utility access
uart Select the CN6 UART path between Smart UART and the Atlas3 SDB interface
pwr Display the status of the onboard power regulators and sequencing
counters Display error counters and statistics for all active ports (counters clear to reset)
flit Configure PCIe Gen6 FLIT mode settings per station
ltssm Display instantaneous LTSSM state for a port, or monitor it continuously
flitdiag Run PCIe Gen6 FLIT diagnostics and continuous monitoring (FLIT BER, lane BER, error counters)
speed Query or set the target link speed (Gen1–Gen6) per port or station and retrain
iicwr Perform an I²C/SMBus write-then-read transaction on an MCIO connector
iicw Perform an I²C/SMBus write transaction on an MCIO connector
i3cwr Perform an I3C write-read transaction on the straddle-mount interface (fixed Channel 8)
i3cw Perform an I3C write transaction on the straddle-mount interface
i3cr Perform an I3C read transaction on the straddle-mount interface
i3c_ccc Send I3C Common Command Code (CCC) operations (MIPI I3C Basic v1.1.1)
mctp Execute MCTP commands (sn, health, pause, resume, abort, status, replay) to a selected slot
packet Send raw MCTP packet data (hex, up to 128 bytes) to a selected slot
ver Display version information for the host card, MCU firmware, and Atlas3 firmware
sysinfo Display a consolidated report: firmware, telemetry, power status, link state, and diagnostics
reset Reset the onboard MCU, a PCIe hierarchy (reset s0), or the Atlas3 switch (reset sw)

Notable command behavior:

  • Firmware updates (fdl): four targets — mini (unmanaged mini SBR), main (unmanaged main SBR), fw (managed switch firmware), and mcu (onboard MCU firmware). The mini, main, and fw commands erase all regions of the Atlas3 switch flash before writing. After upload, power-cycle the card for switch firmware updates; for MCU firmware, use reset instead of a power cycle.
  • Host card modes (setmode): the card stores multiple SBR configuration files, and setmode <1–8> loads the one for the selected mode. All modes run the host-to-golden-finger link in common clock. Modes 1–4 enable Gen6 precoding with MCIO bifurcation of 1×16, 2×8, 4×4, and 8×2 respectively; modes 5–8 disable precoding with the same 1×16, 2×8, 4×4, and 8×2 bifurcations. Verify the active configuration with showmode.
  • Clock spread (spread): spread 1 for 3,000 ppm down-spread (−0.3%), spread 2 for 5,000 ppm down-spread (−0.5%), or spread off.
  • Clock outputs (clk): clk en / clk dis control reference-clock output to the straddle-mount and MCIO interfaces. The change is dynamic (no power cycle), is stored in the MCU and reapplied at next power-on, and does not affect the Atlas3 switch’s own system reference clock.
  • SDB access (sdb, uart): sdb on switches the board from normal MCU/CLI operation to SDB utility mode for host-based Broadcom tools such as SwitchCLID or ARCTIC (distributed under NDA/SLA); sdb off returns to normal CLI operation. uart 0 routes CN6 to Smart UART; uart 1 routes it to SDB (default). Smart UART is supported only in managed firmware mode; SDB works in both modes.
  • FLIT control (flit): flit <all|station 0–3> <on|off> sets FLIT-disable mode; entering flit alone shows per-station state. FLIT mode is required for 64 GT/s operation — disabling FLIT prevents links from training at Gen6.
  • Link-training diagnostics (ltssm, flitdiag, speed): ltssm [-p] <port> [-mon] [interval_ms] [count] shows a port’s current LTSSM state or samples it repeatedly (e.g. ltssm 32 10 100), and ltssm decode explains the state codes. flitdiag [port] [-fber] [-lnber] [-errcnt [0~3]] [clear] reports Gen6 FLIT bit-error rate, per-lane bit-error rate, and FLIT error counters, and can clear them. speed with no arguments reports link speeds; speed <port> <gen1~gen6> or speed stn <0~3> <gen1~gen6> sets a target speed for a port or a whole station and retrains the link (e.g. speed 0 gen5, speed stn 0 5).
  • Link status (showport): reports station, connector/port ID, physical port number, negotiated speed and width, desired (Max) speed and width, status, and DPR state for all USP/DSP ports. Status values: Active (desired and negotiated matched), Idle (no link/device), Degraded (trained below the desired speed or width).
  • Error counters (counters): per-port PortRx, BadTLP, BadDLLP, RecDiag, LinkDown, and FlitError counters.
  • Resets (conrst, reset): conrst <0–8|all> [a|b] sends a 300 ms PERST# pulse (channel A uses MCIO pins B11/B12; channel B uses B29/B30). reset targets the MCU; reset s0 resets the S0 PCIe hierarchy via S0_PCE_PERST_N; reset sw issues SYS_PWR_ON_RST_N to the Atlas3 switch.
  • Board health (lsd, pwr, bist): lsd reports switch temperature, fan RPM, monitored rails (P12V_IN, P1V8_IN, P1V5_IN, P1V2_IN, P0V85_IN, P0V8A_REFCLK, P0V8A0_IN–P0V8A3_IN), and input power — reported under P12VGF_IN when slot-powered or P12VAUX_IN when auxiliary-powered. pwr reports rail enable states, power-good signals, and overall sequencing status. bist checks MCU communication with onboard I²C devices (power regulators, EEPROM, temperature sensor, I/O expanders, I²C multiplexer, clock generators and buffers) and reports OK or FAIL per device and address.

Maintenance and diagnostics

Serial Cables’ manual maps common symptoms to CLI checks:

  • General system check: run sysinfo for firmware, telemetry, power, link state, clock configuration, and device diagnostics in one report.
  • Link not training as expected: run showport to compare negotiated versus desired speed and width (a Degraded status indicates a mismatch), then counters for accumulated port errors. Use ltssm <port> -mon to watch where training stalls, flitdiag <port> -fber or -lnber to check Gen6 FLIT and per-lane error rates, and speed to force a lower target speed and retrain for comparison.
  • Suspected power issue: run pwr for rail enable/power-good/sequencing status and lsd for voltage readings and power consumption.
  • LED13 (red) illuminated: run bist to check onboard I²C device communication and lsd for temperature, voltage, fan, and power telemetry.
  • After a firmware update: run ver to confirm MCU and Atlas3 firmware versions. Atlas3 managed/unmanaged updates require a power cycle; MCU updates are applied with reset.

Frequently asked questions

Each answer below is self-contained.

What is the Serial Cables Atlas3 64-A0 Host Adapter Card?

The Serial Cables Atlas3 64-A0 Host Adapter Card (part number PCI6-AD-x16HI-BG6-64) is a PCIe 6.0 switch-based host adapter from Serial Cables, LLC, built on the Broadcom PEX90064 Atlas3 switch. It fans a host system out to four MCIO x8 (SFF-TA-1016) connectors and one PCIe straddle-mount connector — up to 64 lanes and 40 ports — with an onboard MCU providing a USB-C CLI for configuration, monitoring, diagnostics, and firmware management.

Who makes the Atlas3 64-A0 Host Adapter Card?

The card is made by Serial Cables, LLC, a provider of PCIe and CXL validation and interconnect hardware based in Englewood, Colorado. Support is at support@serialcables.com, sales at sales@serialcables.com, phone +1 (303) 495-2320, and the website is https://serialcables.com/.

What switch silicon does the card use?

The card is built around the Broadcom PEX90064 Atlas3 PCIe Gen 6 switch, supporting up to 64 lanes and 40 ports. Gen6 signaling uses PAM-4 with FLIT mode and Forward Error Correction on Broadcom’s Talon 5 SerDes.

Do I need a Gen6 motherboard or CPU to use it?

No. Because the Atlas3 switch — not the host chipset — is the Gen6 boundary, the card can be installed in an existing Gen5 system and still provide full Gen6 connectivity to devices downstream of the switch. This is the core reason Serial Cables offers the card: Gen6 device testing can begin before Gen6-native host platforms are available.

What is the difference between managed and unmanaged operation?

The adapter supports both. Unmanaged operation runs without managed firmware for transparent fanout behavior, while managed operation loads firmware that enables higher-level switch functions. Firmware for both modes — plus the onboard MCU firmware — is upgraded over the CLI with the fdl command. The Atlas3 heartbeat LED (LED14) blinks when managed firmware is running normally and stays solid when unmanaged firmware is loaded.

How are the four MCIO connectors mapped to PCIe lanes?

CN3 carries lanes 16–23, CN5 carries lanes 24–31, CN4 carries lanes 32–39, and CN2 carries lanes 40–47 of the PEX90064 switch. Each MCIO x8 connector also carries four HCSL reference-clock outputs, two I²C interfaces, and four PERST# signals as sidebands.

How is the card powered, and when is auxiliary power required?

When no device is installed in the straddle-mount connector, the card can run from host PCIe slot power alone, and maximum power consumption is 65 W with Gen6 x64 links. When a device is installed in the straddle-mount connector, the PCIe 12 V 2×6 auxiliary input (CN8) is required — it powers the adapter and cooling assembly and supplies up to 75 W to the straddle-mount device. Serial Cables specifies a 12 V / 20 A, 500 W, 12VHPWR-compliant (16-pin ATX 3.0+) supply for the auxiliary input.

Which USB-C port do I use for the CLI?

Use CN7, the USB Type-C port connected to the onboard MCU — attach a USB-C cable, find the COM port in Device Manager, and open a serial terminal to get the Cmd> prompt. CN6 is a separate debug port exposing the Atlas3 I²C slave interface and a switchable SDB/Smart UART path (selected with the uart command); it is not used for the standard MCU CLI.

How do I update the firmware?

Run fdl with a target: mini or main for the unmanaged SBR firmware images, fw for managed switch firmware, or mcu for the onboard MCU firmware. Confirm with Y when prompted, then send the BIN file over XMODEM from the terminal emulator (File → Transfer → XMODEM → Send in Tera Term). Power-cycle the card to apply switch firmware; apply MCU firmware with the reset command instead. Note that mini, main, and fw erase all regions of the switch flash before writing.

How do I connect the card to a Gen6 JBOF?

Use MCIO6-8X-2X8B Y-cables between the host card’s MCIO ports and the JBOF enclosure, giving access to eight single-port PCIe x4 E3 SSDs. The manual’s integration table lists the PCI5-ENC8-E3-08 8-bay E3 JBOF as the target; Serial Cables documents the same Y-cable connection scheme for its Gen6 HYDRA 8-Bay Passive E3 JBOF (PCI6-ENC8-E3-08).

How do I attach EDSFF SSDs directly, without an enclosure?

Use the MCIO6-8X-EDSFFX2-1X4 cable from one of the card’s MCIO x8 interfaces. Direct-attach supports E1.S, E1.L, E2, and E3 form-factor SSDs for bench testing.

Can the card drive a physical PCIe x16 slot for add-in cards?

Yes — pair it with the Serial Cables PCI6-AD-MX8-X16 slot adapter. Two MCIO x8 ports connect to one adapter over MCIO6-8X-8X-xM cables, and each adapter presents one PCIe Gen6 x16 slot; a single 64-A0 host card can drive two such adapters for external add-in-card testing.

What do the LEDs mean?

LED13 (red) is a system-error indicator covering watchdog expiration, BISR errors, firmware signature-authentication failure, and double-bit ECC errors. LED14 (blue) is the Atlas3 heartbeat — blinking for healthy managed firmware, solid for unmanaged firmware. LED15 (green) blinks when the MCU is active. The blue link-speed LEDs (LED9–LED12) stay solid on when the first port of their interface links at Gen6; the red link-width LEDs (LED1–LED6) stay off when the expected width is achieved and light when a port trains narrow.

How do I check whether every link trained at the expected speed and width?

Run showport, which lists each USP/DSP port’s station, connector, physical port number, negotiated speed and width, desired (Max) values, DPR state, and status. Active means the link matched the desired configuration; Degraded means it trained below it; Idle means no device was detected.

What is Dynamic Port Reconfiguration (DPR)?

DPR lets the internal and external MCIO interfaces support different PCIe link widths — including multiple x2 connections — without requiring a full switch reset, allowing lane groups to be split or consolidated around the devices being tested.

What are the setmode precoding and bifurcation options?

setmode loads one of eight stored SBR configurations, all using common clock on the host golden-finger link. Modes 1–4 enable Gen6 precoding with MCIO bifurcation of 1×16, 2×8, 4×4, and 8×2; modes 5–8 disable precoding with the same four bifurcations. showmode confirms the active configuration.

How do I configure spread-spectrum clocking?

The spread command sets the Atlas3 reference-clock spread behavior: spread 1 applies 3,000 ppm down-spread (−0.3%), spread 2 applies 5,000 ppm down-spread (−0.5%), and spread off disables spread spectrum.

Does disabling FLIT mode affect Gen6 link training?

Yes. The flit command controls whether a port advertises FLIT-mode support during link training, and FLIT mode is required for operation at 64 GT/s — enabling FLIT-disable mode (flit all on, or per station 0–3) will prevent links from training at Gen6 speeds. It does not modify the FLIT capability reported in PCIe configuration registers.

How do I debug a Gen6 link that will not train?

Start with showport to see negotiated versus desired speed and width, then run ltssm <port> -mon to watch the LTSSM state and see where training stalls (ltssm decode explains the state codes). For links that train but run with errors, flitdiag <port> -fber and -lnber report Gen6 FLIT and per-lane bit-error rates, and counters shows accumulated port errors. speed <port> <gen1~gen6> sets a lower target speed and retrains, so you can check whether the link is stable below Gen6. These commands were added in manual Revision 1.1.

What is SDB mode used for?

sdb on switches the board from normal MCU/CLI operation to expose the Atlas3 Serial Debug Bridge for host-based Broadcom utilities such as SwitchCLID or ARCTIC (Broadcom tools distributed under NDA/SLA); sdb off returns the board to normal CLI operation. Only one mode is active at a time.

Can I query NVMe devices out of band through the card?

Yes — the CLI includes MCTP support. mctp <slot> sn requests a device’s serial number and mctp <slot> health requests health status, and the packet command sends raw MCTP packet data (hex, up to 128 bytes) to a selected slot for lower-level device communication and debugging.

Does the card support I3C sideband access?

Yes — the i3cwr, i3cw, and i3cr commands perform I3C write-read, write, and read transactions with devices on the PCIe straddle-mount interface (CN1) over a fixed I3C Channel 8, and i3c_ccc runs MIPI I3C Basic v1.1.1 Common Command Codes such as ENTDAA, SETDASA, RSTDAA, GETPID, and SETNEWDA for device discovery and dynamic-address management.

How do I run a board-level diagnostic?

Run bist, which checks MCU communication with the card’s onboard I²C devices — power regulators, EEPROM, the temperature sensor, I/O expanders, the I²C multiplexer, and clock generators/buffers — and reports OK or FAIL per device and address. sysinfo consolidates firmware versions, telemetry, power status, PCIe link state, and diagnostics into a single report.

About Serial Cables and the PCIe 6.0 interconnect family

Serial Cables, LLC is a provider of high-performance interconnect and validation hardware for PCIe and CXL development, serving hyperscale, enterprise storage, and silicon-validation environments. The Atlas3 64-A0 Host Adapter Card is part of Serial Cables’ family of PCIe 6.0 host cards built on Broadcom Atlas3 and Microchip silicon, sold alongside PCIe 6.0/CXL 3.x retimers (Broadcom, Marvell, and Credo silicon) and a Phison-based linear redriver, the Gen6 HYDRA 8-Bay Passive E3 JBOF and its Hydra Command Center management software, MCIO-to-slot expansion adapters such as the PCI6-AD-MX8-X16, EDSFF adapters, M.2-to-E3 adapters, and validated PCIe 6.0/Gen7 cabling. Serial Cables is also the exclusive Quarch reseller for the U.S. and Mexico.

Disambiguation and related products

  • The Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64) described here uses the 64-lane Broadcom PEX90064. It is distinct from the Serial Cables PCIe 6.0 MCIO Host Card (PCI6-AD-x16HI-BG6-80-B0), built on the 80-lane PEX90080, and from the PCI6-AD-x16HI-BG6-144, built on the 144-lane PEX90144 — all three are Broadcom Atlas3-family host cards with different lane/port counts; station, port, and CON mappings differ between them.
  • Serial Cables’ store page titles this card ‘Gen6 x16 – 4× x8 MCIO Host Card w/ 1×16 Straddle Mount Connector (B0 64-lane Switch),’ while the manual cover names it the ‘Atlas3 64-A0 Host Adapter Card’; both refer to the same SKU, PCI6-AD-x16HI-BG6-64.
  • The manual’s JBOF integration table lists the PCI5-ENC8-E3-08 (Gen5) 8-bay E3 JBOF as a target system; the Gen6 counterpart in the current lineup is the Gen6 HYDRA 8-Bay Passive E3 JBOF (PCI6-ENC8-E3-08), which uses the same MCIO6-8X-2X8B Y-cable connection scheme.
  • CN6 and CN7 are both USB Type-C but are not interchangeable: CN7 is the MCU CLI port used for all standard commands and firmware updates, while CN6 exposes the Atlas3 I²C slave interface and a selectable SDB/Smart UART debug path.
  • MCIO (SFF-TA-1016) is the cabled connector standard used on CN2–CN5; the straddle-mount connector (CN1) is a board-edge-style interface for a directly seated device, not a cable port.
  • The FLIT mode controlled by the flit command is the PCIe Gen6 FLIT (Flow Control Unit) operating mode required at 64 GT/s; it is unrelated to the card’s firmware-update (fdl) process.

Source and contact

This information is drawn from the Serial Cables PCIe 6.0 MCIO Host Card Technical Manual (Atlas3 64-A0 Host Adapter Card, PCI6-AD-x16HI-BG6-64), Revision 1.1 (November 2026), published by Serial Cables, LLC, and the product page on serialcables.com.

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