Serial Cables Atlas3 32-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-32)

The Serial Cables Atlas3 32-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-32) is a PCIe 6.0 switch-based host adapter built on the Broadcom PEX90032 Atlas3 switch — up to 32 lanes fanned out from a x16 host slot to two MCIO x8 connectors, with an onboard MCU CLI for switch configuration, telemetry, link diagnostics, and firmware management.

What it is

The Serial Cables Atlas3 32-A0 Host Adapter Card is a PCIe Gen 6 adapter built around the Broadcom PEX90032 Atlas3 switch, supporting up to 32 PCIe lanes. It connects a host system to external PCIe devices through two right-angle MCIO x8 (SFF-TA-1016) connectors, giving 16 downstream lanes behind a x16 golden-finger host link. It is manufactured by Serial Cables, LLC (Englewood, Colorado, USA), and its part number / SKU is PCI6-AD-x16HI-BG6-32.

The adapter supports both unmanaged operation (without managed firmware) and managed operation (with firmware). An onboard microcontroller provides command-line interface (CLI) access over USB Type-C for switch configuration, device management, diagnostics, and troubleshooting, and the switch adds non-transparent port support, peer-to-peer data transfers, DMA, and PCIe hot-plug functionality. Gen 6 operation uses FLIT mode with Forward Error Correction (FEC) for 64 GT/s links.

In one sentence: the Atlas3 32-A0 Host Adapter Card is a compact Broadcom PEX90032-based PCIe 6.0 host adapter that fans a x16 host slot out to two MCIO x8 cable connectors, with dual USB-C management, per-connector PERST#/clock/I²C sidebands, and an MCU CLI for full switch control — managed or unmanaged.

Like the larger Atlas3 host cards, the 32-A0 lets engineers begin Gen6 testing without waiting for Gen6-native host platforms: installed in an existing Gen5 system, the card provides Gen6 connectivity downstream of the switch, so endpoints behind the Atlas3 — JBOFs, EDSFF SSDs, or add-in cards on expansion fixtures — train and run at Gen6 even though the host itself is a generation behind.

Why it exists

PCIe validation has traditionally been gated on the host: traffic is routed through the CPU and chipset, so testing Gen6 devices meant waiting for Gen6-capable motherboards, CPUs, and BIOS support. A switch-based host adapter breaks that dependency by making the switch — not the host — the Gen6 boundary. The Atlas3 32-A0 is the smallest member of Serial Cables’ Atlas3 host-card family: where the 64-, 80-, and 144-lane cards add more MCIO ports and a straddle-mount device connector, the 32-A0 provides a single x16 of Gen6 downstream connectivity on a short 167 mm board, running from slot power alone. It suits validation and qualification engineers who need switch-level visibility — per-port link status, LTSSM monitoring, FLIT error rates, register access, firmware control — for one x16 worth of devices, without the size or power budget of the larger cards.

Key facts

• Product name: Serial Cables Atlas3 32-A0 Host Adapter Card
• Part number / SKU: PCI6-AD-x16HI-BG6-32
• Manufacturer: Serial Cables, LLC (Englewood, Colorado, USA)
• Category: PCIe 6.0 switch-based host adapter card
• PCIe switch: Broadcom PEX90032 Atlas3 — up to 32 lanes, two x16 stations
• Host interface: PCIe Gen6 x16 golden finger
• Downstream connectivity: 2 × right-angle MCIO x8 (SFF-TA-1016)
• Operating modes: Managed and unmanaged
• Advanced PCIe features: Non-transparent ports, peer-to-peer transfers, DMA channels, hot-plug
• Management: Onboard MCU with USB-C CLI (CN3); second USB-C (CN2) for Atlas3 I²C slave and switchable SDB/Smart UART debug
• Maximum power consumption: 55 W (Gen6 x32 links)
• Operating temperature: 0 °C to +40 °C
• Dimensions: 167 × 69 × 44 mm (L × H × T), including heatsink
• Documentation: User’s Manual Revision 1.0 (November 2026)

Hardware specifications

Connectors, lane assignments, and port mapping

Each MCIO x8 connector carries eight PCIe lanes plus sideband signals: four dedicated PCIe HCSL reference-clock outputs (pins A8/A9, A11/A12, A26/A27, A29/A30), two dedicated I²C interfaces (pins B8/B9 and B26/B27), and four PERST# signals (pins B11, B12, B29, B30). Connector designators are silk-screened on the PCB.

The card identifies interfaces by station, port, and connector (CON) number. The PEX90032 has two stations, each supporting up to 16 PCIe lanes. CON numbers are used by the conrst, iicw, and iicwr commands:

For register-level access, each port’s register block is offset by 0x8000. Base addresses on this card: MCIO Port 0 at 0x60800000 and golden finger Port 32 at 0x60900000.

LED indicators

System status LEDs

Link speed LEDs (blue) — LED6 (golden finger) and LED7 (first MCIO port) blink at a rate tied to the negotiated PCIe generation, stay solid at Gen6, and stay off when no link is detected:

Link width LEDs (red) — these remain off when the expected link width is achieved: LED3 (golden finger, off at x16) and LED9 (MCIO, off at 1×16, 2×8, 4×4, or 8×2). A lit width LED indicates a port trained below its expected width. Use showport for detailed negotiated speed and width.

Power

Maximum power consumption is 55 W with Gen6 x32 links. Unlike the larger Atlas3 host cards, the 32-A0 has no straddle-mount device connector and its connector list includes no auxiliary power input, so the card runs from host PCIe slot power. The lsd command reports the card’s input voltage, current, and power, and pwr reports power-rail status. Power down the host system before installing, removing, or re-cabling the card.

Key features

• Broadcom PEX90032 Atlas3 switch: up to 32 Gen6 lanes in two x16 stations, with FLIT mode and FEC for 64 GT/s operation.
• Two MCIO x8 connectors: cable connectivity to JBOFs, direct-attached EDSFF SSDs, and slot-expansion fixtures.
• Compact, slot-powered design: 167 × 69 mm board, 55 W maximum, no auxiliary power cable.
• Managed and unmanaged operation: run without managed firmware for transparent fanout, or load managed firmware for higher-level switch functions.
• Advanced PCIe functionality: non-transparent ports, true peer-to-peer data transfer, DMA channels, and hot-plug support.
• Selectable precoding and MCIO bifurcation: eight stored SBR configurations cover precoding on or off with 1×16, 2×8, 4×4, or 8×2 MCIO bifurcation.
• Full MCU CLI over USB-C: firmware updates, register access, per-port link status, error counters, live LTSSM monitoring, Gen6 FLIT error-rate diagnostics, per-port link-speed control, reference-clock and spread-spectrum control, SMBus and MCTP sideband access, and board diagnostics.
• Gen6 testing without a Gen6 host: installed in an existing Gen5 system, the switch provides Gen6 connectivity downstream.

Gen6 JBOF connectivity

The host adapter connects to an external 8-bay E3 JBOF enclosure using MCIO6-8X-2X8B Y-cables; the manual states one host card supports eight single-port x4 E3/E1.S SSDs. The manual’s application diagram labels the target system as the PCI5-ENC8-E3-08 8-bay E3 JBOF; Serial Cables’ Gen6 counterpart is the Gen6 HYDRA 8-Bay Passive E3 JBOF (PCI6-ENC8-E3-08), which uses the same Y-cable scheme.

Direct-attached EDSFF SSDs

EDSFF SSDs can be connected directly to the adapter’s MCIO interfaces without an external enclosure, using the MCIO6-8X-EDSFFX2-1X4 cable (MCIO x8 SFF-TA-1016 74-pin to two EDSFF SFF-TA-1009 56-pin 1C). This configuration supports E1.S, E1.L, E2, and E3 form-factor SSDs for bench testing and drive qualification.

PCIe Gen6 slot expansion

The card can extend PCIe connectivity to a physical add-in-card slot outside the host chassis. Its two MCIO x8 ports connect to a PCI6-AD-MX8-X16 expansion adapter over MCIO6-8X-8X-xM cables, and the adapter provides a PCIe Gen6 x16 slot for add-in-card testing.

Command-line interface (CLI)

The onboard MCU provides command-line access for switch configuration, diagnostics, and firmware management over CN3 (USB Type-C). CN2 is not used for the standard MCU CLI — it exposes the Atlas3 I²C slave interface and a selectable SDB/Smart UART path instead. To connect: attach a USB-C cable from the host computer to CN3, identify the assigned COM port in Device Manager, and open a serial terminal (Tera Term, PuTTY, or minicom on Linux); a successful connection displays the cmd> prompt. All commands are typed in lower case.

Notable command behavior:

• Firmware updates (fdl): five targets — mini (unmanaged mini SBR), main (unmanaged main SBR), fw (managed switch firmware), mcu (onboard MCU firmware), and config (a multi-config SBR bundle written to the MCU’s QSPI flash). Press y to proceed or Ctrl+X to cancel, then send the BIN file over XMODEM. The mini, main, and fw commands erase all regions of the Atlas3 switch flash before writing. Power-cycle the card after switch firmware updates; for MCU firmware, use reset instead.
• Host card modes (setmode, bifmode): the card stores multiple SBR configuration files, and setmode <1–8> loads the one for the selected mode. All modes run the host-to-golden-finger link in common clock. Modes 1–4 enable Gen6 precoding with MCIO bifurcation of 1×16, 2×8, 4×4, and 8×2 respectively; modes 5–8 disable precoding with the same four bifurcations. setmode requires hardware Rev. 1.1 or later. bifmode [1–8] changes the bifurcation mode by burning the selected SBR from the MCU’s QSPI flash into the switch flash. Verify the active configuration with showmode.
• Clock spread (spread): sets the Atlas3 fundamental clock to common clock or spread-spectrum — spread 1 for 3,000 ppm down-spread (−0.3%), spread 2 for 5,000 ppm down-spread (−0.5%), or spread off.
• Clock outputs (clk): clk en / clk dis control reference-clock output to all MCIO ports. The change takes effect without a power cycle, is stored in the MCU and reapplied at next power-on, and does not affect the Atlas3 switch’s own reference clock, which is always enabled.
• SDB access (sdb, uart): sdb on switches the board from normal MCU/CLI operation to SDB utility mode for host-based Broadcom tools such as SwitchCLID or ARCTIC (distributed by Broadcom under NDA/SLA); sdb off returns to normal CLI operation. uart 0 routes CN2 to Smart UART; uart 1 routes it to SDB (default). The setting is stored and applied at the next power cycle. Smart UART is supported only in managed firmware; SDB works in both modes.
• FLIT control (flit): flit <all|0|2> <on|off> sets FLIT-disable mode for all ports or for station 0 or 2. FLIT mode is required for 64 GT/s operation — disabling FLIT prevents links from training at Gen6. It does not change the FLIT capability reported in PCIe configuration registers.
• Link-training diagnostics (ltssm, flitdiag, speed): ltssm [-p] <port> [-mon] [interval_ms] [count] shows a port’s current LTSSM state or samples it repeatedly (e.g. ltssm 32 10 100), and ltssm decode explains the state codes. flitdiag [port] [-fber] [-lnber] [-errcnt [0~3]] [clear] reports Gen6 FLIT bit-error rate, per-lane bit-error rate, and FLIT error counters, and can clear them (e.g. flitdiag 0 -fber). speed with no arguments reports link speeds; speed <port> <gen1~gen6> or speed stn <0|2> <gen1~gen6> sets a target speed for a port or a whole station and retrains the link (e.g. speed 32 6, speed stn 0 gen4).
• Link status (showport): reports station, connector, physical port number, negotiated and desired speed and width, and status for all USP/DSP ports. Status values: Active (desired and negotiated matched), Idle (no physical link detected), Degraded (desired and negotiated speed or width do not match).
• Error counters (counters): per-port error counters, including a FLIT error count that increments on countable events defined in the Flit Error Counter Control Register and decrements at a fixed rate based on encoding and link width. counters clear resets them.
• Sideband access (iicwr, iicw, mctp, packet): SMBus reads and writes target a device by I²C address and CON number (0–3), up to 128 bytes — e.g. iicwr d4 0 8 0 reads 8 bytes from register 0 of address 0xD4 on CON 0. Channel A is the I²C interface on MCIO pins B8/B9; channel B is on B26/B27. mctp <slot> sn and mctp <slot> health query a device’s serial number and health; packet sends raw MCTP packet data.
• Resets (conrst, reset): conrst <0–3|all> [channel] sends a 300 ms PERST# pulse on MCIO pins B11/B12/B29/B30. reset resets the MCU; reset s0 and reset s1 reset a PCIe hierarchy (S0_PCE_PERST0 / S1_PCE_PERST0); reset sw issues SYS_PWR_ON_RST_N, a system power-on reset of the Atlas3 switch.
• Board health (lsd, pwr, bist): lsd reports the temperature near the Atlas3 switch, fan RPM, critical on-board voltages, and input voltage, current, and power. pwr reports power status. bist checks MCU communication with onboard I²C devices such as the EEPROM, I²C I/O expander, I²C multiplexer, clock generator, and clock buffer.

Maintenance and diagnostics

Common symptoms map to these CLI checks:

• General system check: run sysinfo, which runs ver, lsd, clk, pwr, showport, and bist in one report.
• Link not training as expected: run showport to compare negotiated versus desired speed and width (a Degraded status indicates a mismatch), then counters for accumulated port errors. Use ltssm <port> -mon to watch where training stalls, flitdiag <port> -fber or -lnber to check Gen6 FLIT and per-lane error rates, and speed to force a lower target speed and retrain for comparison.
• Wrong link width on the MCIO connectors: check the active configuration with showmode and select the matching bifurcation with setmode (or bifmode).
• Suspected power issue: run pwr for power status and lsd for voltage readings and power consumption.
• LED2 (red) illuminated: run bist to check onboard I²C device communication and lsd for temperature, voltage, fan, and power telemetry.
• After a firmware update: run ver to confirm MCU and Atlas3 firmware versions. Atlas3 managed/unmanaged updates require a power cycle; MCU updates are applied with reset.

Frequently asked questions

Each answer below is self-contained.

About Serial Cables and the PCIe 6.0 interconnect family

Serial Cables, LLC is a provider of high-performance interconnect and validation hardware for PCIe and CXL development, serving hyperscale, enterprise storage, and silicon-validation environments. The Atlas3 32-A0 Host Adapter Card is part of Serial Cables’ family of PCIe 6.0 host cards built on Broadcom Atlas3 and Microchip silicon, sold alongside PCIe 6.0/CXL 3.x retimers (Broadcom, Marvell, and Credo silicon) and a Phison-based linear redriver, the Gen6 HYDRA 8-Bay Passive E3 JBOF and its Hydra Command Center management software, MCIO-to-slot expansion adapters such as the PCI6-AD-MX8-X16, EDSFF adapters, M.2-to-E3 adapters, and validated PCIe 6.0/Gen7 cabling. Serial Cables is also the exclusive Quarch reseller for the U.S. and Mexico.

Disambiguation and related products

• The Atlas3 32-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-32) described here uses the 32-lane Broadcom PEX90032. It is distinct from the Atlas3 64-A0 Host Adapter Card (PCI6-AD-x16HI-BG6-64) on the 64-lane PEX90064, the PCIe 6.0 MCIO Host Card (PCI6-AD-x16HI-BG6-80-B0) on the 80-lane PEX90080, and the PCI6-AD-x16HI-BG6-144 on the 144-lane PEX90144 — all are Broadcom Atlas3-family host cards with different lane counts; connector designators, station, port, and CON mappings differ between them.
• On the 32-A0, the USB-C ports are CN2 (Atlas3 debug/UART) and CN3 (MCU CLI), and the MCIO connectors are CN5 and CN6. On the 64-A0 the same functions are on CN6/CN7 and CN2–CN5 respectively, so commands and documentation that name connectors are not interchangeable between the two cards.
• The manual’s JBOF application diagram labels the target as the PCI5-ENC8-E3-08 (Gen5) 8-bay E3 JBOF; the Gen6 counterpart in the current lineup is the Gen6 HYDRA 8-Bay Passive E3 JBOF (PCI6-ENC8-E3-08), which uses the same MCIO6-8X-2X8B Y-cable connection scheme.
• MCIO (SFF-TA-1016) is the cabled connector standard used on CN5 and CN6.
• The FLIT mode controlled by the flit command is the PCIe Gen6 FLIT (Flow Control Unit) operating mode required at 64 GT/s; it is unrelated to the card’s firmware-update (fdl) process.

Source and contact

This information is drawn from the Serial Cables Atlas3 32 Host Adapter Card User’s Manual (PCI6-AD-x16HI-BG6-32), Revision 1.0 (November 2026), published by Serial Cables, LLC.

• Support: support@serialcables.com
• Sales: sales@serialcables.com
• Phone: +1 (303) 495-2320
• Website: https://serialcables.com/